Co-Synthesis of Dynamically Reconfigurable SOPCs Specified by Condi- tional Task Graphs

In this work the co-synthesis method, that optimizes dynamically reconfigurable multiprocessor SOPC system architectures, is presented. The algorithm maximizes speed of a SOPC system, taking into consideration the space constraints of the FPGA. The algorithm starts with the initial solution, where all tasks are assigned to only one general purpose processor module. Next, it produces new solutions using iterative improvement methods. To the best of authors’ knowledge, it is the first algorithm that takes into consideration mutually exclusive tasks in optimization of dynamically reconfigurable systems. Such tasks are specified using conditional task graphs. Partially reconfigurable FPGAs enable reuse of the same hardware resources for mutually exclusive tasks. In this way, the area occupied by an embedded system can be decreased and free space may be used for other purposes. It was shown that the presented approach can also increase the performance of a SOPC system.